公开(公告)号：US09570144B2

公开(公告)日：2017-02-14

申请号：US15046820

申请日：2016-02-18

Applicant: Rambus Inc.

Inventor： Richard Perego ,  Thomas Vogelsang ,  John Brooks

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/408 ,  G11C2211/4061

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract translation: 本公开描述了DRAM架构和刷新控制器，其允许与指向DRAM设备的正常行激活命令同时调度DRAM设备的机会性刷新。 每个激活命令提供了在没有调度冲突的情况下刷新存储器设备内的另一独立行（即字线）的“机会”。

公开(公告)号：US20170178713A1

公开(公告)日：2017-06-22

申请号：US15391295

申请日：2016-12-27

Applicant: Rambus Inc.

Inventor： Richard Perego ,  Thomas Vogelsang ,  John Brooks

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/408 ,  G11C2211/4061

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

公开(公告)号：US20160217843A1

公开(公告)日：2016-07-28

申请号：US15046820

申请日：2016-02-18

Applicant: Rambus Inc.

Inventor： Richard Perego ,  Thomas Vogelsang ,  John Brooks

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/408 ,  G11C2211/4061

Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

Abstract translation: 本公开描述了DRAM架构和刷新控制器，其允许与指向DRAM设备的正常行激活命令同时调度DRAM设备的机会性刷新。 每个激活命令提供了在没有调度冲突的情况下刷新存储器设备内的另一独立行（即字线）的“机会”。