公开(公告)号：US11500986B2

公开(公告)日：2022-11-15

申请号：US17028831

申请日：2020-09-22

Applicant: Rambus Inc.

Inventor： Simon Hoerder

IPC: G06F21/55

Abstract: A masked logic gate protected against side-channel attacks using Boolean masking with d+1 shares for each input variable, where d is an integer at least equal to 1 representing the protection order is described. The masked logic gate includes a first input configured to receive a number of shares yj (j=0, 1, 2 . . . ); a second input configured to receive (d+1)2 shares xi (i=0, 1, 2 . . . ) representative of an intermediate result output by one layer of a tree of gates implementing low-latency masking with a protection order of d; and a (d+1)-share output obtained by applying a logic function of the masked logic gate to the shares of the first and second inputs using domain-oriented masking.

公开(公告)号：US20210097175A1

公开(公告)日：2021-04-01

申请号：US17028831

申请日：2020-09-22

Applicant: Rambus Inc.

Inventor： Simon Hoerder

IPC: G06F21/55

Abstract: A masked logic gate protected against side-channel attacks using Boolean masking with d+1 shares for each input variable, where d is an integer at least equal to 1 representing the protection order is described. The masked logic gate includes a first input configured to receive a number of shares yj (j=0, 1, 2 . . . ); a second input configured to receive (d+1)2 shares xi (i=0, 1, 2 . . . ) representative of an intermediate result output by one layer of a tree of gates implementing low-latency masking with a protection order of d; and a (d+1)-share output obtained by applying a logic function of the masked logic gate to the shares of the first and second inputs using domain-oriented masking.