公开(公告)号：US20160210070A1

公开(公告)日：2016-07-21

申请号：US14990668

申请日：2016-01-07

Applicant: Renesas Electronics Corporation

Inventor： Takashi KURAFUJI ,  Akira AWATANI

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0688

Abstract: An information processing apparatus according to the present invention includes: at least one flash memory including a data storage region that stores data and an erase count storage region that stores erase count data indicating the number of times that the data is erased in the data storage region; and a control circuit that is connected between a processor and the at least one flash memory. The control circuit allows changes of data stored in the data storage region by the processor and suppresses changes of the erase count data stored in the erase count storage region by the processor.

Abstract translation: 根据本发明的信息处理设备包括：至少一个闪速存储器，其包括存储数据的数据存储区域和擦除计数存储区域，其存储指示数据在数据存储区域中被擦除的次数的擦除计数数据 ; 以及连接在处理器和所述至少一个闪速存储器之间的控制电路。 控制电路允许由处理器改变存储在数据存储区域中的数据，并且通过处理器抑制存储在擦除计数存储区域中的擦除计数数据的改变。