公开(公告)号：US20170309728A1

公开(公告)日：2017-10-26

申请号：US15468862

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA ,  Tetsuo ITO ,  Koji OGATA ,  Hideki AONO

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/266 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66568 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/78603

Abstract: In a process of implanting ions of an n-type impurity for threshold control into a semiconductor substrate surrounded by an element isolation portion, a resist pattern is formed such that the resist pattern covers a divot formed at a boundary portion of the element isolation portion with an SOI layer. Thus, since ions of the n-type impurity are not implanted into the divot, an etching rate of the divot in a cleaning process or the like is not accelerated, and etching can be suppressed. As a result, a BOX layer is prevented from becoming thin, so that degradation of a TDDB characteristic of the BOX layer can be prevented.