公开(公告)号：US07298667B2

公开(公告)日：2007-11-20

申请号：US11202314

申请日：2005-08-12

申请人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

发明人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

IPC分类号： G11C8/00

CPC分类号： G11C29/023 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。

公开(公告)号：US20060077751A1

公开(公告)日：2006-04-13

申请号：US11202314

申请日：2005-08-12

申请人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

发明人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

IPC分类号： G11C8/02

CPC分类号： G11C29/023 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。

公开(公告)号：US06879533B2

公开(公告)日：2005-04-12

申请号：US10609071

申请日：2003-06-27

申请人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

发明人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： An integrated circuit memory device can include a memory cell array having a plurality of memory cells, and a bit line sense amplifier configured to amplify data on a pair of bit lines from a memory cell of the memory cell array and to provide the amplified data on a data line and a complementary data line. An active load circuit includes a first load device electrically connected between the data line and a voltage source wherein an electrical resistance of the first load device is varied responsive to a voltage level of the data line. The active load circuit also includes a second load device electrically connected between the complementary data line and the voltage source wherein an electrical resistance of the second load device is varied responsive to a voltage level of the complementary data line. Related methods are also discussed.

摘要翻译： 集成电路存储器件可以包括具有多个存储单元的存储单元阵列和位线读出放大器，该位线读出放大器被配置为放大来自存储单元阵列的存储单元的一对位线上的数据，并将放大数据提供到 数据线和补充数据线。 有源负载电路包括电连接在数据线和电压源之间的第一负载装置，其中第一负载装置的电阻响应于数据线的电压电平而变化。 有源负载电路还包括电连接在互补数据线和电压源之间的第二负载装置，其中第二负载装置的电阻响应补充数据线的电压电平而变化。 还讨论了相关方法。

公开(公告)号：US06777987B2

公开(公告)日：2004-08-17

申请号：US10394682

申请日：2003-03-21

申请人： Moo-sung Chae ,  Chi-wook Kim ,  Sung-min Seo

发明人： Moo-sung Chae ,  Chi-wook Kim ,  Sung-min Seo

IPC分类号： H03K300

CPC分类号： H03K5/14 ,  H03K5/12 ,  H03K19/01721 ,  H04L25/0288

摘要： A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

摘要翻译： 信号线驱动电路包括反相缓冲器，脉冲发生器，第一信号缓冲器和第二信号缓冲器。 这里，反相缓冲器接收输入信号，并包括连接到信号线的输出端以驱动信号线。 脉冲发生器接收输入信号以产生脉冲信号。 第一信号缓冲器具有连接到脉冲发生器的输出端子的控制端子和连接到信号线的节点的输入/输出端子。 第一信号缓冲器响应于第一控制信号减小在信号线上传播的信号的上升转变时间。 第二信号缓冲器具有连接到脉冲发生器的输出端的控制端子和连接到信号线的节点的输入/输出端子。 第二信号缓冲器响应于第一控制信号减少在信号线上传播的信号的下降转变时间。

公开(公告)号：US20050078545A1

公开(公告)日：2005-04-14

申请号：US10941446

申请日：2004-09-15

申请人： Moo-sung Chae ,  Hyung-chan Choi

发明人： Moo-sung Chae ,  Hyung-chan Choi

IPC分类号： G11C11/40 ,  G11C8/00 ,  G11C11/408 ,  G11C29/46

CPC分类号： G11C7/1066 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/46 ,  G11C2029/1204

摘要： There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal. A column selection line signal can be generated without an increase in circuit logic, depending on a type of operation mode. Accordingly, it is possible to effectively realize CCD=1tCK in a semiconductor memory device, which operates in the DDR2 mode, in a test operation mode.

摘要翻译： 提供了用于控制列选择线信号的生成的方法和电路。 该方法包括确定当前模式是正常操作模式还是测试操作模式; 当当前模式是测试操作模式时，接收激活的测试操作模式信号和激活的第一时钟信号，并输出具有与第一时钟信号的激活时间成比例的激活时间的列选择线信号; 并且当当前模式是正常操作模式时，响应于所激活的第一时钟信号输出被激活的列选择线信号，并响应于激活的第二时钟信号被停用。 第一时钟信号的激活时间与外部时钟信号的激活时间成比例。 在测试操作模式下，在外部时钟信号的一个周期内执行命令。 根据操作模式的类型，可以产生列选择线信号而不增加电路逻辑。 因此，可以在测试操作模式中在以DDR2模式工作的半导体存储器件中有效地实现CCD = 1tCK。

公开(公告)号：US06992949B2

公开(公告)日：2006-01-31

申请号：US10941446

申请日：2004-09-15

申请人： Moo-sung Chae ,  Hyung-chan Choi

发明人： Moo-sung Chae ,  Hyung-chan Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1066 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/46 ,  G11C2029/1204

摘要： There are provided a method and circuit for controlling generation of a column selection line signal. The method includes determining whether a current mode is a normal operation mode or a test operation mode; receiving an activated test operation mode signal and an activated first clock signal and outputting a column selection line signal with an activation time proportional to an activation time of the first clock signal, when the current mode is the test operation mode; and outputting the column selection line signal that is activated in response to the activated first clock signal and is deactivated in response to an activated second clock signal, when the current mode is the normal operation mode. An activation time of the first clock signal is proportional to that of an external clock signal. In the test operation mode, a command is performed during one period of the external clock signal. A column selection line signal can be generated without an increase in circuit logic, depending on a type of operation mode. Accordingly, it is possible to effectively realize CCD=1tCK in a semiconductor memory device, which operates in the DDR2 mode, in a test operation mode.

摘要翻译： 提供了用于控制列选择线信号的生成的方法和电路。 该方法包括确定当前模式是正常操作模式还是测试操作模式; 当当前模式是测试操作模式时，接收激活的测试操作模式信号和激活的第一时钟信号，并输出具有与第一时钟信号的激活时间成比例的激活时间的列选择线信号; 并且当当前模式是正常操作模式时，响应于所激活的第一时钟信号输出被激活的列选择线信号，并响应于激活的第二时钟信号被停用。 第一时钟信号的激活时间与外部时钟信号的激活时间成比例。 在测试操作模式下，在外部时钟信号的一个周期内执行命令。 根据操作模式的类型，可以产生列选择线信号而不增加电路逻辑。 因此，可以在测试操作模式中在以DDR2模式工作的半导体存储器件中有效地实现CCD = 1tCK。