公开(公告)号：US20150102350A1

公开(公告)日：2015-04-16

申请号：US14479557

申请日：2014-09-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Soo SO ,  Jong Hyun CHOI ,  Shin Moon KANG ,  IL Hun SEO

IPC: H01L27/12

CPC classification number: H01L27/1237 ,  H01L27/1255 ,  H01L27/1274

Abstract: A thin film transistor array panel includes a plurality of pixels on a substrate. Each pixel of the plurality of pixels includes a driving and a switching thin film transistor. The driving thin film transistor includes a first semiconductor including first source and drain regions, a first gate electrode overlapping the first semiconductor, a gate insulating layer between the first semiconductor and the first gate electrode, an oxide layer between the first semiconductor and the gate insulating layer, and first source and drain electrodes. The switching thin film transistor includes a second semiconductor including second source and drain regions, a second gate electrode overlapping the second semiconductor, and second source and drain electrodes. The switching thin film transistor includes the gate insulating layer between the second semiconductor and the second gate electrode. The gate insulating layer contacts an upper portion of the second semiconductor.

Abstract translation: 薄膜晶体管阵列面板包括在基板上的多个像素。 多个像素中的每个像素包括驱动和开关薄膜晶体管。 驱动薄膜晶体管包括：包括第一源极和漏极区域的第一半导体，与第一半导体重叠的第一栅极电极，在第一半导体和第一栅极电极之间的栅极绝缘层，第一半导体和栅极绝缘之间的氧化物层 层和第一源极和漏极。 开关薄膜晶体管包括包括第二源极和漏极区域的第二半导体，与第二半导体重叠的第二栅极电极以及第二源极和漏极电极。 开关薄膜晶体管包括在第二半导体和第二栅电极之间的栅极绝缘层。 栅绝缘层接触第二半导体的上部。