公开(公告)号：US20230116188A1

公开(公告)日：2023-04-13

申请号：US17943448

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsub RIE ,  Eunseok SHIN ,  Youngdon CHOI ,  Changsoo YOON ,  Hyunyoon CHO ,  Junghwan CHOI

IPC: G11C11/4096 ,  H03M1/12

Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.