公开(公告)号：US20190258775A1

公开(公告)日：2019-08-22

申请号：US16404910

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MOON-SU KIM ,  Naya Ha ,  Jong-ku Kang ,  Andrew Paul Hoover

IPC: G06F17/50

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.