Multi-Stage Delay-Locked Loop Phase Detector
    1.
    发明申请
    Multi-Stage Delay-Locked Loop Phase Detector 有权
    多级延迟锁相环检测器

    公开(公告)号:US20140266370A1

    公开(公告)日:2014-09-18

    申请号:US13840675

    申请日:2013-03-15

    CPC classification number: H03K5/1504

    Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

    Abstract translation: 相位检测器包括包括多个触发器的相位传播器电路。 每个触发器包括时钟输入,其被配置为接收相对于在多个触发器中的其它触发器接收的时钟信号的相位具有不同相位的时钟信号。 相位检测器还包括耦合到多个触发器中的每个触发器的时钟输入的相位控制器。 相位控制器被配置为向多个触发器提供时钟信号的不同相位,使得不同相位相对于彼此成指数地缩放。

    Multi-stage delay-locked loop phase detector
    2.
    发明授权
    Multi-stage delay-locked loop phase detector 有权
    多级延迟锁相环相位检测器

    公开(公告)号:US09172361B2

    公开(公告)日:2015-10-27

    申请号:US13840675

    申请日:2013-03-15

    CPC classification number: H03K5/1504

    Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

    Abstract translation: 相位检测器包括包括多个触发器的相位传播器电路。 每个触发器包括时钟输入,其被配置为接收相对于在多个触发器中的其它触发器接收的时钟信号的相位具有不同相位的时钟信号。 相位检测器还包括耦合到多个触发器中的每个触发器的时钟输入的相位控制器。 相位控制器被配置为向多个触发器提供时钟信号的不同相位,使得不同相位相对于彼此成指数地缩放。

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