公开(公告)号：US11387216B2

公开(公告)日：2022-07-12

申请号：US16907094

申请日：2020-06-19

申请人： SK hynix Inc.

发明人： Jin Ho Kim ,  Young Ki Kim ,  Sang Hyun Sung ,  Sung Lae Oh ,  Byung Hyun Jun

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L49/02

摘要： A semiconductor memory device includes a plurality of first pads disposed in one surface of a memory chip which includes a memory cell array and a plurality of row lines coupled to the memory cell array, and coupled to the row lines, respectively; and a plurality of second pads disposed in one surface of a circuit chip which is boned to the one surface of the memory chip, coupled to pass transistors, respectively, of the circuit chip, and bonded to the first pads, respectively. The second pads are aligned with the pass transistors, with the same pitch as a pitch of the pass transistors.

公开(公告)号：US11315914B2

公开(公告)日：2022-04-26

申请号：US16890653

申请日：2020-06-02

申请人： SK hynix Inc.

发明人： Sang Hyun Sung ,  Young Ki Kim ,  Jin Ho Kim ,  Byung Hyun Jun

IPC分类号： H01L27/11582 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11573 ,  H01L23/528

摘要： A semiconductor memory device includes: a first pad layer in a surface of a memory chip including a cell region in which a memory cell array coupled to a plurality of row lines and a step region including staggered step portions of the plurality of row lines, and including a plurality of first pads that are coupled to the step portions; a second pad layer in a surface of a circuit chip bonded to the surface of the memory chip, and having a plurality of second pads coupled to a plurality of pass transistors defined in the circuit chip; a first redistribution line disposed in the first pad layer that couples one of the step portions and one of the pass transistors; and a second redistribution line disposed in the second pad layer that couples another one of the step portions and another one of the pass transistors.

公开(公告)号：US11239166B2

公开(公告)日：2022-02-01

申请号：US16876008

申请日：2020-05-16

申请人： SK hynix Inc.

发明人： Jeong Hwan Kim ,  Jin Ho Kim ,  Byung Hyun Jun ,  Chang Woon Choi

IPC分类号： H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/1157

摘要： A semiconductor memory device includes a cell region defined with vertical channels which pass through electrode layers and interlayer dielectric layers alternately stacked; a step region disposed adjacent to the cell region in a first direction, and defined with contacts coupled to the electrode layers extending in different lengths; a first opening passing through the electrode layers and the interlayer dielectric layers in the step region; a second opening passing through the electrode layers and the interlayer dielectric layers in the cell region; under wiring lines coupled with a peripheral circuit defined on a substrate; top wiring lines disposed over the electrode layers and the interlayer dielectric layers, and coupled with the contacts; and vertical vias coupling the under and top wiring lines, wherein the vertical vias include first vertical vias which pass through the first opening and second vertical vias which pass through the second opening.