公开(公告)号：US20160127158A1

公开(公告)日：2016-05-05

申请号：US14891454

申请日：2014-06-17

Applicant: ST-ERICSSON SA

Inventor： Kimmo KOLI

IPC: H04L25/49 ,  H04B7/06

CPC classification number: H04L25/4917 ,  H04B7/06 ,  H04L25/0272 ,  H04L25/0292

Abstract: A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.

Abstract translation: 用于N线数字接口的接收机，其中N是超过2的整数，具有N个输入端，公共节点和N个检测级。 N个检测级中的每一个具有耦合在公共节点和N个输入端子中的相应一个的电阻元件，以及比较器，具有耦合到N个输入端子中的相应一个的第一输入端和耦合到该公共端口的第二输入端 节点。

公开(公告)号：US20160127159A1

公开(公告)日：2016-05-05

申请号：US14892739

申请日：2014-06-17

Applicant: ST-ERICSSON SA

Inventor： Kimmo KOLI

IPC: H04L25/49 ,  H04B7/06

CPC classification number: H04L25/4917 ,  H04B7/06 ,  H04L7/0079 ,  H04L25/0272 ,  H04L25/0292

Abstract: A receiver (100) for a three-wire digital interface, comprises a first resistive element (R1) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R2) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R3) coupled between a third input terminal (C) and a third junction node (JC). A network (70) comprising first second and third network terminals (71, 72, 73) is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C1) has a non-inverting input (10) coupled to the first input terminal (A), an inverting input (12) coupled to the second junction node (JB), and an output (14) coupled to a first output terminal (AJ). A second comparator (C2) has a non-inverting input (20) coupled to the AK first input terminal (A), an inverting input (22) coupled to the third junction node (JC), and an output (24) coupled to a second output terminal (AK). A third comparator (C3) has a non-inverting input (30) coupled to the second input terminal (B), an inverting input (32) coupled to the third junction node (JC), and an output (34) coupled to a third output terminal (BJ). A fourth comparator (C4) has a non-inverting input (40) coupled to the second input terminal (B), an inverting input (42) coupled to the first junction node (JA), and an output (44) coupled to a fourth output terminal (BK). A fifth comparator (C5) has a non-inverting input (50) coupled to the third input terminal (C), an inverting input (52) coupled to the first junction node (JA), and an output (54) coupled to a fifth output terminal (CJ). A sixth comparator (C6) has a non-inverting input (60) coupled to the third input terminal (C), an inverting input (62) coupled to the second junction node (JB), and an N output (64) coupled to a sixth output terminal (CK).