Abstract:
A low-power-mode unit connected in parallel with a low-dropout regulator to provide a low-power mode includes a power P-MOS transistor, a differential amplifier, and an analog synchronization loop. The analog synchronization loop is configured to add a variable voltage offset depending on a total current at the output such that, in a high-power mode, the low-power unit current flowing through the P-MOS transistor is not zero, while being substantially smaller than the low-dropout regulator current flowing through the low-dropout regulator, and smaller than a predetermined value.
Abstract:
The present invention concerns a low dropout (LDO) regulator of regulating an output signal, the LDO regulator comprising an input stage (15) and an output stage (17), the input stage being adapted to receive a reference signal (VREF) and a feed-back signal (VF) depending on an output signal (VOUT), and to output an intermediate signal based on the feedback signal and on the reference signal, wherein the LDO regulator further comprises a gain stage (16) having a given gain value, which is configurable and wherein the output signal is regulated based on the gain value of the gain stage and on the intermediate signal.
Abstract:
The present invention concerns a low dropout (LDO) regulator of regulating an output signal, the LDO regulator comprising an input stage (15) and an output stage (17), the input stage being adapted to receive a reference signal (VREF) and a feed-back signal (VF) depending on an output signal (VOUT), and to output an intermediate signal based on the feedback signal and on the reference signal, wherein the LDO regulator further comprises a gain stage (16) having a given gain value, which is configurable and wherein the output signal is regulated based on the gain value of the gain stage and on the intermediate signal.