M-ary sequence clock spreading
    1.
    发明授权
    M-ary sequence clock spreading 有权
    M序列时钟扩展

    公开(公告)号:US08941419B2

    公开(公告)日:2015-01-27

    申请号:US14240571

    申请日:2012-09-27

    Applicant: ST-Ericsson SA

    Inventor: Fabien Journet

    CPC classification number: H03K21/08 H04B15/06

    Abstract: The invention concerns a device for providing a spread frequency clock signal, comprising: —an input (51) to receive a first clock signal having a first frequency; —a programmable clock divider (52) to generate the spread frequency clock signal from the first clock signal; —a first Feedback Shift Register (21), FSR, comprising at least one stage, the FSR being adapted to generate any of an odd number M of different values, the FSR being adapted to pseudo-randomly generate a first sequence of first output values, each corresponding to one of said M different values, and to provide a first output value, according to the sequence, during each clock cycle of the spread frequency clock signal; —a control unit (22) adapted to select a division factor of the programmable clock divider based on the first output value of the FSR during each clock cycle of the spread frequency clock signal; —an output (53) for providing the spread frequency clock signal.

    Abstract translation: 本发明涉及一种用于提供扩展频率时钟信号的装置,包括: - 输入(51),用于接收具有第一频率的第一时钟信号; - 可编程时钟分频器(52),用于从所述第一时钟信号产生所述扩频时钟信号; - 第一反馈移位寄存器(21),FSR,包括至少一级,所述FSR适于生成不同值的奇数M中的任何一个,所述FSR适于伪随机生成第一输出值的第一序列 ,每个对应于所述M个不同值中的一个,并且在扩展频率时钟信号的每个时钟周期期间根据该序列提供第一输出值; - 控制单元(22),适于在扩展频率时钟信号的每个时钟周期期间基于FSR的第一输出值选择可编程时钟分频器的分频系数; - 用于提供扩频时钟信号的输出(53)。

    M-ARY Sequence Clock Spreading
    2.
    发明申请
    M-ARY Sequence Clock Spreading 有权
    M-ARY序列时钟传播

    公开(公告)号:US20140247073A1

    公开(公告)日:2014-09-04

    申请号:US14240571

    申请日:2012-09-27

    Applicant: ST-Ericsson SA

    Inventor: Fabien Journet

    CPC classification number: H03K21/08 H04B15/06

    Abstract: The invention concerns a device for providing a spread frequency clock signal, comprising: -an input (51) to receive a first clock signal having a first frequency; -a programmable clock divider (52) to generate the spread frequency clock signal from the first clock signal; -a first Feedback Shift Register (21), FSR, comprising at least one stage, the FSR being adapted to generate any of an odd number M of different values, the FSR being adapted to pseudo-randomly generate a first sequence of first output values, each corresponding to one of said M different values, and to provide a first output value, according to the sequence, during each clock cycle of the spread frequency clock signal; -a control unit (22) adapted to select a division factor of the programmable clock divider based on the first output value of the FSR during each clock cycle of the spread frequency clock signal; -an output (53) for providing the spread frequency clock signal.

    Abstract translation: 本发明涉及一种用于提供扩展频率时钟信号的装置,包括: - 输入(51),用于接收具有第一频率的第一时钟信号; - 可编程时钟分频器(52),用于从所述第一时钟信号产生所述扩频时钟信号; - 第一反馈移位寄存器(21),FSR,包括至少一级,所述FSR适于生成不同值的奇数M中的任何一个,所述FSR适于伪随机生成第一输出值的第一序列 ,每个对应于所述M个不同值中的一个,并且在扩展频率时钟信号的每个时钟周期期间根据该序列提供第一输出值; - 控制单元(22),适于在扩展频率时钟信号的每个时钟周期期间基于FSR的第一输出值选择可编程时钟分频器的分频系数; - 用于提供扩频时钟信号的输出(53)。

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