公开(公告)号：US09058049B2

公开(公告)日：2015-06-16

申请号：US13865494

申请日：2013-04-18

Applicant: ST-Ericsson SA

Inventor： Alexandre Pons ,  Gilles Chevalier

IPC: G05F1/00 ,  H02H7/00 ,  H02H9/00 ,  G05F1/46 ,  G05F1/565

CPC classification number: G05F1/46 ,  G05F1/565

Abstract: A low-power-mode unit connected in parallel with a low-dropout regulator to provide a low-power mode includes a power P-MOS transistor, a differential amplifier, and an analog synchronization loop. The analog synchronization loop is configured to add a variable voltage offset depending on a total current at the output such that, in a high-power mode, the low-power unit current flowing through the P-MOS transistor is not zero, while being substantially smaller than the low-dropout regulator current flowing through the low-dropout regulator, and smaller than a predetermined value.

Abstract translation: 与低压差稳压器并联连接以提供低功率模式的低功率模式单元包括功率P-MOS晶体管，差分放大器和模拟同步环路。 模拟同步环路被配置为根据输出端的总电流增加可变电压偏移，使得在大功率模式中流过P-MOS晶体管的低功率单元电流不为零，同时基本上 小于流过低压降稳压器的低压差稳压器电流，并小于预定值。