公开(公告)号：US20040196067A1

公开(公告)日：2004-10-07

申请号：US10249353

申请日：2003-04-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Razak Hossain ,  Marco Cavalli

IPC: H03K019/20

CPC classification number: H03K3/356156 ,  H03K3/0375

Abstract: A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Abstract translation: 可测试的脉冲触发静态触发器。 只有当测试使能输入为低电平时，脉冲发生器才产生数据使能触发脉冲，只有当测试使能输入为高电平时，扫描测试才能使能触发脉冲。 数据使能触发脉冲控制触发器输入的数据，而扫描测试使能触发脉冲控制触发器的扫描测试输入。 触发器由包括两个锁存器的选择电路组成，每个锁存器包括反相器和传输门。 一个锁存器接收数据输入，另一个锁存器接收扫描测试输入。 数据使能触发脉冲控制传输门接收数据输入，扫描测试触发脉冲控制传输门接收扫描测试输入。 触发器还包括由反馈逆变器和静态锁存器组成的保持器电路。

公开(公告)号：US20040158807A1

公开(公告)日：2004-08-12

申请号：US10248721

申请日：2003-02-12

Applicant: STMICROELECTRONICS, INC.

Inventor： Razak Hossain ,  Fabrizio Viglione ,  Bernard Bourgin

IPC: G06F017/50

CPC classification number: G06F17/505

Abstract: A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).

Abstract translation: 使用静态逻辑电路合成工具（12）从源电路定义（14）合成多米诺逻辑电路设计（18）的方法包括使用电路合成工具（12）生成初步的多米诺逻辑电路（26）设计，以及 通过将静态单元设计替换为在初级多米诺逻辑电路设计中具有相同功能的多米诺骨牌单元设计来优化初步多米诺逻辑电路设计的属性（30）。