公开(公告)号：US09323633B2

公开(公告)日：2016-04-26

申请号：US13852223

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Marco Brambilla ,  Ulderic Lacour ,  Cecilia Ozdemir

IPC: G06F11/00 ,  G06F11/25 ,  G01R31/3177 ,  G06F11/267

CPC classification number: G06F11/267

Abstract: A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers.

Abstract translation: 双主控制器包括多个JTAG数据寄存器，包括存储指示标准JTAG或处理器控制的操作模式的信息的控制器模式寄存器。 JTAG TAP控制器通过标准测试访问端口接收控制信号，处理器控制器通过外部处理器总线接收处理器控制信号。 响应于JTAG模式选择信号，选择多路复用器输出标准JTAG访问端口或外部处理器总线上的信号。 逻辑电路响应于JTAG信号被激活或控制器模式寄存器中指示标准JTAG模式的信息激活JTAG模式选择信号，并且响应于JTAG信号被去激活而停用JTAG模式选择信号 控制器模式寄存器指示处理器 - 控制器模式。 指令解码器和多路复用器电路从选择多路复用器施加控制信号以控制JTAG数据寄存器。