公开(公告)号：US20210083637A1

公开(公告)日：2021-03-18

申请号：US16984445

申请日：2020-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Valle ,  Flavio Polloni

IPC: H03G3/30 ,  H04R29/00 ,  H04R3/00 ,  H03F3/183

Abstract: A method of monitoring electrical loads is disclosed. In an embodiment the method includes generating a first voltage signal and a second voltage signal, the second voltage signal in quadrature to the first voltage signal, injecting one of the first voltage signal or the second voltage signal into a signal propagation path towards an electrical load, sensing a current signal flowing through the electrical load as a result of the one of the first voltage signal or the second voltage signal injected into the signal propagation path and processing the first voltage signal, the second voltage signal and the sensed current signal.

公开(公告)号：US11183981B2

公开(公告)日：2021-11-23

申请号：US16984445

申请日：2020-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Valle ,  Flavio Polloni

IPC: H03G3/30 ,  H03F3/183 ,  H04R3/00 ,  H04R29/00

Abstract: A method of monitoring electrical loads is disclosed. In an embodiment the method includes generating a first voltage signal and a second voltage signal, the second voltage signal in quadrature to the first voltage signal, injecting one of the first voltage signal or the second voltage signal into a signal propagation path towards an electrical load, sensing a current signal flowing through the electrical load as a result of the one of the first voltage signal or the second voltage signal injected into the signal propagation path and processing the first voltage signal, the second voltage signal and the sensed current signal.

公开(公告)号：US10333538B1

公开(公告)日：2019-06-25

申请号：US16004192

申请日：2018-06-08

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Stefano Valle ,  Edoardo Lauri ,  Angelo Poloni

IPC: H03H7/30 ,  H03M1/06 ,  H03H17/04 ,  H04L25/03

Abstract: The present disclosure is directed to a method and system for compensating mismatches among sub-converters in a time interleaved analog digital converter structure. A digital finite impulse response (FIR) equalization filtering unit is coupled to outputs of the sub-converters. The FIR filtering unit includes a digital FIR filter dedicated to each sub-converter. The FIR filtering coefficient is adapted specifically for each sub-converter to achieve a compensation for sub-converter mismatches and inter-symbol interference (ISI) equalization.