公开(公告)号：US20190068193A1

公开(公告)日：2019-02-28

申请号：US16142627

申请日：2018-09-26

Applicant: STMicroelectronics, Inc.

Inventor： Chetan BISHT ,  Harry SCRIVENER

IPC: H03K19/0175 ,  G06F17/50 ,  H01L23/528 ,  H01L23/50

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.