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公开(公告)号：US11686992B2
公开(公告)日：2023-06-27
申请号：US17476668
申请日：2021-09-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
CPC classification number: G02F1/2257 , G02F1/025 , G02F1/035 , G02F2202/103
Abstract: A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.
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Patent Agency Ranking
公开(公告)号：US12032265B2
公开(公告)日：2024-07-09
申请号：US18317705
申请日：2023-05-15
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
CPC classification number: G02F1/2257 , G02F1/025 , G02F1/035 , G02F2202/103
Abstract: A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.
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公开(公告)号：US20230280630A1
公开(公告)日：2023-09-07
申请号：US18317705
申请日：2023-05-15
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
CPC classification number: G02F1/2257 , G02F1/025 , G02F1/035 , G02F2202/103
Abstract: A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.
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公开(公告)号：US20220004076A1
公开(公告)日：2022-01-06
申请号：US17476668
申请日：2021-09-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
Abstract: A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.
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公开(公告)号：US11150533B2
公开(公告)日：2021-10-19
申请号：US16931090
申请日：2020-07-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.
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公开(公告)号：US20210018815A1
公开(公告)日：2021-01-21
申请号：US16931090
申请日：2020-07-16
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frédéric Boeuf , Cyrille Barrera
Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.
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