公开(公告)号：US10892291B2

公开(公告)日：2021-01-12

申请号：US16285306

申请日：2019-02-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sonarith Chhun ,  Gregory Imbert

IPC: H01L27/146 ,  H01L21/84 ,  H01L23/48 ,  H01L21/762 ,  H01L27/06 ,  H01L27/12 ,  H01L21/3065 ,  H01L23/00 ,  H01L23/552 ,  H01L29/94

Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

公开(公告)号：US20190088695A1

公开(公告)日：2019-03-21

申请号：US15707009

申请日：2017-09-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sonarith Chhun ,  Gregory Imbert

IPC: H01L27/146 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/3065

Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.