公开(公告)号：US20220229796A1

公开(公告)日：2022-07-21

申请号：US17716481

申请日：2022-04-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Francois CLOUTE ,  Christophe TABA

IPC: G06F13/28

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

公开(公告)号：US20200311001A1

公开(公告)日：2020-10-01

申请号：US16830626

申请日：2020-03-26

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Francois CLOUTE ,  Christophe TABA

IPC: G06F13/28

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.