公开(公告)号：US20210173568A1

公开(公告)日：2021-06-10

申请号：US17111778

申请日：2020-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald BRIAT ,  Stephane MARMEY

IPC: G06F3/06

Abstract: The integrity of a memory is checked by: storing data representative of an operation to be executed in the memory; executing the operation; and erasing the data once the execution is complete.

公开(公告)号：US20210173469A1

公开(公告)日：2021-06-10

申请号：US17111877

申请日：2020-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald BRIAT

IPC: G06F1/3234 ,  G06F3/06

Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

公开(公告)号：US20230129599A1

公开(公告)日：2023-04-27

申请号：US18084669

申请日：2022-12-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Gerald BRIAT

IPC: G06F1/3234 ,  G06F3/06

Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

公开(公告)号：US20200081776A1

公开(公告)日：2020-03-12

申请号：US16562025

申请日：2019-09-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gerald BRIAT ,  Antoine DE-MUYNCK ,  Alessandro BASTONI ,  Stephane MARMEY

IPC: G06F11/10 ,  G11C17/00

Abstract: An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.