公开(公告)号：US12074605B2

公开(公告)日：2024-08-27

申请号：US18151332

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Aradhana Kumari

IPC: H03K5/1252 ,  H03K5/135

CPC classification number: H03K5/1252 ,  H03K5/135

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.