公开(公告)号：US20240320359A1

公开(公告)日：2024-09-26

申请号：US18614171

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy

IPC: G06F21/62 ,  G06F9/50

CPC classification number: G06F21/6218 ,  G06F9/5044

Abstract: A system-on-a-chip includes at least one slave resource, a resource isolation system, and a countermeasure circuit capable of and intended to limit the operation of the system against potential anomalies, and, for the at least one slave resource, a protection circuit configured to block or transmit transactions addressed to the resource depending on access rights of the resource and of the transaction. The protection circuit is configured to generate and directly communicate an alert signal to the countermeasure circuit in the event of a transaction being blocked.

公开(公告)号：US20240406163A1

公开(公告)日：2024-12-05

申请号：US18678831

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy ,  Maxime Mere ,  Frédéric Jouault

IPC: H04L9/40 ,  G06F21/10 ,  H04L9/32

Abstract: A method for life cycle management of a system-on-chip having functions includes multi-user ownership management listing owners of the functions in a directory, and allocating rights of a function over the life cycle of the system-on-chip, according to a configuration command including identifying the function, identifying a right of ownership or access to the function, and a signature of the owner of the function.

公开(公告)号：US10025726B2

公开(公告)日：2018-07-17

申请号：US14526686

申请日：2014-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Herve Sibert ,  Loic Pallardy

IPC: G06F12/00 ,  G06F12/1036 ,  G06F12/1009

Abstract: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.

公开(公告)号：US20150143072A1

公开(公告)日：2015-05-21

申请号：US14526686

申请日：2014-10-29

Applicant: STMicroelectronics International N.V.

Inventor： Herve Sibert ,  Loic Pallardy

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F2212/657

Abstract: A memory management unit (MMU) may manage address translations. The MMU may obtain a first intermediate physical address (IPA) based on a first virtual address (VA) relating to a first memory access request. The MMU may identify, based on the first IPA, a first memory page entry in a second address translation table. The MMU may store, in a second cache memory, a first IPA-to-PA translation based on the identified first memory page entry. The MMU may store, in the second cache memory and in response to the identification of the first memory page entry, one or more additional IPA-to-PA translations that are based on corresponding one or more additional memory page entries in the second address translation table. The one or more additional memory page entries may be contiguous to the first memory page entry.

Abstract translation: 内存管理单元（MMU）可以管理地址转换。 MMU可以基于与第一存储器访问请求相关的第一虚拟地址（VA）获得第一中间物理地址（IPA）。 MMU可以基于第一IPA识别第二地址转换表中的第一存储器页条目。 MMU可以在第二高速缓冲存储器中存储基于所识别的第一存储器页条目的第一IPA到PA转换。 MMU可以在第二高速缓冲存储器中存储并且响应于第一存储器页条目的标识，基于第二地址转换中的对应的一个或多个附加存储器页条目的一个或多个附加的IPA到PA转换 表。 一个或多个附加存储器页条目可以与第一存储器页条目相邻。

公开(公告)号：US20240370382A1

公开(公告)日：2024-11-07

申请号：US18652555

申请日：2024-05-01

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy ,  Vincent Berthelot

IPC: G06F12/14

Abstract: The system on chip includes a memory controller adapted to receive transactions containing transaction information defining an access to a memory, the memory controller being configured to store the transaction information in a command register, and to control the access to the memory from the content of the command register. The memory controller includes verification circuitry configured to determine the access to the memory depending on a comparison between the transaction information stored in the command register and a list of special information defining special transactions.