公开(公告)号：US20250080100A1

公开(公告)日：2025-03-06

申请号：US18240585

申请日：2023-08-31

Applicant: STMicroelectronics International N.V.

Inventor： Sandor PETENYI ,  Lukas BURYANEC

IPC: H03K17/082 ,  H03K5/24

Abstract: A power circuit includes a power transistor coupled between input and output nodes and receiving a control signal. A current sensing current senses a power current provided by the power transistor to the output node and generates a sense voltage. A voltage sensing circuit senses a drain-to-source voltage of the power transistor and generates a VDS sense current. A safe operating area (SOA) shaping circuit has a gain set by an adjustable resistance that is dynamically adjusted based upon the VDS sense current, the SOA shaping circuit applying the gain to the sense voltage to produce an adjusted sense voltage. A timing circuit generates an intermediate voltage by comparing the adjusted sense voltage and a first reference. An output comparator asserts a flag in response to the intermediate voltage becoming at least equal to a second reference. The control signal is modified in response to assertion of the flag.