公开(公告)号：US20190331733A1

公开(公告)日：2019-10-31

申请号：US16505174

申请日：2019-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US20230128466A1

公开(公告)日：2023-04-27

申请号：US17510602

申请日：2021-10-26

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA ,  Tripti GUPTA

IPC: G01R31/3177 ,  G06F1/28 ,  G01R31/317

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

公开(公告)号：US20200064405A1

公开(公告)日：2020-02-27

申请号：US16671933

申请日：2019-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Manish SHARMA

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/27 ,  G06F11/267

Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.