公开(公告)号：US11635465B2

公开(公告)日：2023-04-25

申请号：US17504139

申请日：2021-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Rohit Goel ,  Anand Kumar Mishra ,  Rajnish Garg

IPC: G01R31/3185

Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.