Digital clock generator circuit with built-in frequency and duty cycle control
    1.
    发明申请
    Digital clock generator circuit with built-in frequency and duty cycle control 有权
    数字时钟发生器电路,内置频率和占空比控制

    公开(公告)号:US20020079943A1

    公开(公告)日:2002-06-27

    申请号:US09988883

    申请日:2001-11-20

    Inventor: Prashant Dubey

    CPC classification number: H03K3/0315 G06F1/04 G06F1/08 H03K3/017

    Abstract: A digital clock generator circuit with built-in frequency and duty cycle control may include a pulse generator for generating a start pulse. The pulse generator may be connected to a ring oscillator to generate multiple signals having a specified frequency and programmable duty cycles. The oscillator may further be connected to a multiplexer which selectively connects one output of the ring oscillator to a final output to produce a signal of the specified frequency and specified duty cycle. The duty cycle may be adjustable over a wide range and across the full frequency band of operation.

    Abstract translation: 具有内置频率和占空比控制的数字时钟发生器电路可以包括用于产生起始脉冲的脉冲发生器。 脉冲发生器可以连接到环形振荡器以产生具有指定频率和可编程占空比的多个信号。 振荡器还可以连接到选择性地将环形振荡器的一个输出连接到最终输出以产生指定频率和指定占空比的信号的多路复用器。 占空比可以在宽范围和整个工作频带范围内调节。

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