公开(公告)号：US20040153923A1

公开(公告)日：2004-08-05

申请号：US10667199

申请日：2003-09-18

Applicant: STMicroelectronics Pvt, Ltd.

Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

IPC: G01R031/28

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value nullnnull. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract translation: 一种用于重新加载在可编程逻辑器件配置期间检测到错误的帧的改进的方法和装置。 FPGA的配置数据帧被加载到FPGA的帧寄存器，并且还加载到检测错误的错误检测电路。 错误计数器值由设备维护，并且每当检测到帧的错误时递增。 递增值由具有预定阈值“n”的比较器电路进行比较。 如果发现匹配，则配置过程将中止，否则数据帧将重新加载到配置存储器中，再次传输到帧寄存器并重新检查错误。 如果在重新加载的帧中没有检测到错误，错误计数器值将被复位，下一个帧被加载，直到FPGA配置过程结束。