Cascode drive circuitry
    1.
    发明授权
    Cascode drive circuitry 有权
    串联驱动电路

    公开(公告)号:US08729927B2

    公开(公告)日:2014-05-20

    申请号:US13657930

    申请日:2012-10-23

    CPC classification number: H03K17/102

    Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed

    Abstract translation: 驱动电路包括具有设计最大电压V2的开关晶体管和具有设计最大电压V1的共源共栅晶体管,其中共源共栅晶体管是与开关晶体管串联耦合的源极 - 漏极。 电路还包括耦合在中间电压节点和共源共栅晶体管的栅极之间的电流源。 如果驱动电路是低端驱动器,则中间电压节点接收设置在高电源电压Vhigh以下的中间电压Vmed,并满足以下条件:a)Vmed <= V2和b)Vhigh-Vmed <= V1。 如果驱动电路是高侧驱动器,则中间电压节点接收低于高电源电压的中间电压Vmed,并且符合以下条件:a)Vmed <= V1和b)Vhigh-Vmed <= V2。 该电路可以通过将高侧驱动器和低侧驱动器串联耦合而构造为推挽驱动器。

    CASCODE DRIVE CIRCUITRY
    2.
    发明申请
    CASCODE DRIVE CIRCUITRY 有权
    CASCODE驱动电路

    公开(公告)号:US20130169344A1

    公开(公告)日:2013-07-04

    申请号:US13657930

    申请日:2012-10-23

    CPC classification number: H03K17/102

    Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed

    Abstract translation: 驱动电路包括具有设计最大电压V2的开关晶体管和具有设计最大电压V1的共源共栅晶体管,其中共源共栅晶体管是与开关晶体管串联耦合的源极 - 漏极。 电路还包括耦合在中间电压节点和共源共栅晶体管的栅极之间的电流源。 如果驱动电路是低端驱动器,则中间电压节点接收设置在高电源电压Vhigh以下的中间电压Vmed,并满足以下条件:a)Vmed <= V2和b)Vhigh-Vmed <= V1。 如果驱动电路是高侧驱动器,则中间电压节点接收低于高电源电压的中间电压Vmed,并且符合以下条件:a)Vmed <= V1和b)Vhigh-Vmed <= V2。 该电路可以通过将高侧驱动器和低侧驱动器串联耦合而构造为推挽驱动器。

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