公开(公告)号：US20020141241A1

公开(公告)日：2002-10-03

申请号：US10068565

申请日：2002-02-05

Applicant: STMicroelectronics S.r.I.

Inventor： Irene Babudri ,  Mauro Giacomini

IPC: G11C016/26

CPC classification number: G11C29/24 ,  G11C16/28

Abstract: A memory device implements a reading operation that comprises: providing first and second additional memory cells whose threshold voltage values correspond to a maximum value and a minimum value of a distribution of threshold voltages of a cell array of the memory device; programming the first and second additional memory cells with predetermined first and second logic values; simultaneously reading a logic contents of the first and second additional memory cells, and data to be read in the cell array; comparing the logic contents of the first and second additional memory cells, as read during the reading step, with the first and second predetermined logic values; generating a result signal of the comparison step, such a result signal having a first value in the event of the logic contents of the first and second additional memory cells, as read during the reading step, matching the first and second predetermined logic values, respectively, and having a second value in the event of the logic contents of the first and second additional memory cells, as read during the reading step, failing to match the first and second predetermined logic values, respectively.

Abstract translation: 存储器件实现读取操作，其包括：提供其阈值电压值对应于存储器件的单元阵列的阈值电压分布的最大值和最小值的第一和第二附加存储器单元; 以预定的第一和第二逻辑值对第一和第二附加存储器单元进行编程; 同时读取第一和第二附加存储器单元的逻辑内容以及要在单元阵列中读取的数据; 将在读取步骤期间读取的第一和第二附加存储器单元的逻辑内容与第一和第二预定逻辑值进行比较; 生成比较步骤的结果信号，在读取步骤期间读取第一和第二附加存储器单元的逻辑内容的情况下具有第一值的结果信号分别与第一和第二预定逻辑值相匹配 并且在读取步骤期间读取的第一和第二附加存储器单元的逻辑内容的第二值分别不匹配第一和第二预定逻辑值。