公开(公告)号：US20220308615A1

公开(公告)日：2022-09-29

申请号：US17702362

申请日：2022-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： Barbaro MARANO ,  Mario CHIRICOSTA

IPC: G05F3/26 ,  H03F3/45

Abstract: A cell includes a first pair and a second pair of MOS transistors. Each of the first pair and second pair of MOS transistors have drain electrodes coupled to a respective common input node. Each of the first pair and second pair of MOS transistors includes a diode-connected MOS transistor and a latched MOS transistor. The latched MOS transistors of the first pair and second pair of MOS transistors have cross-coupled gate and drain electrodes. Source electrodes of the diode connected MOS transistors from the first pair and second pair of MOS transistors are coupled to a first current output common node to output a current to a first current collecting circuit. Source source electrodes of the latched MOS transistors of the first pair and second pair of MOS transistors are coupled to a second current output common node to output a current to a second current collecting circuit.