公开(公告)号：US12135668B2

公开(公告)日：2024-11-05

申请号：US18056012

申请日：2022-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Castellano ,  Francesco Bruni ,  Luca Gandolfi ,  Marco Leo

IPC: G06F3/00 ,  G06F13/40

Abstract: A processor includes a synchronous circuit including a plurality of processing stages, wherein each processing stage includes a selection data bus; and an asynchronous circuit coupled to each selection data bus, wherein the asynchronous circuit includes an asynchronous state machine whose states correspond to a process phase or a plurality of circuits, wherein the asynchronous circuit further includes a selectable delay circuit whose delay is determined by a present state of the asynchronous state machine, and wherein the asynchronous circuit is configured for generating a plurality of processing stage clock signals each having a selectable delay provided by the selectable delay circuit.