公开(公告)号：US20040229438A1

公开(公告)日：2004-11-18

申请号：US10746881

申请日：2003-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Moscatelli ,  Claudia Raffaglio ,  Alessandra Merlini ,  M. P. Galbiati

IPC: H01L021/8234

CPC classification number: H01L29/6659 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/66659 ,  H01L29/7835

Abstract: A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the substrate. A first dielectric layer is formed on the substrate. A first semiconductor material layer is then formed on the first dielectric layer, in the first portion. A stack structure comprising a second dielectric layer, second semiconductor layer, and low-resistance layer is then formed over the substrate. First ports are defined in the second semiconductor layer and the low-resistance layer to provide gate regions of the vertical or lateral MOS transistors. The second semiconductor layer and the low-resistance layer are then removed from the first portion of the substrate by using the second dielectric layer as a screen. Second ports in the second dielectric layer and the second semiconductor layer are then defined to provide gate regions for the CMOS transistors. The gate region of the vertical or lateral transistors is then covered with a protective layer. A low-resistance layer is then formed on the gate regions of the CMOS transistors.

Abstract translation: 公开了一种在公共半导体衬底上分别在衬底的至少第一和第二部分上形成CMOS晶体管和垂直或横向MOS晶体管的工艺。 在基板上形成第一电介质层。 在第一部分中，在第一介电层上形成第一半导体材料层。 然后在衬底上形成包括第二电介质层，第二半导体层和低电阻层的堆叠结构。 第一端口被限定在第二半导体层和低电阻层中，以提供垂直或横向MOS晶体管的栅极区域。 然后通过使用第二介电层作为屏幕，从基板的第一部分去除第二半导体层和低电阻层。 然后限定第二介电层和第二半导体层中的第二端口以为CMOS晶体管提供栅极区域。 然后用保护层覆盖垂直或横向晶体管的栅极区域。 然后在CMOS晶体管的栅极区域上形成低电阻层。