公开(公告)号：US20220214384A1

公开(公告)日：2022-07-07

申请号：US17378226

申请日：2021-07-16

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Dino COSTANZO ,  Cheng Pan CAI ,  Xi Yu XU

IPC: G01R19/25 ,  H02P27/08 ,  H02M1/00 ,  G01R15/14 ,  H02M7/5387

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

公开(公告)号：US20210172983A1

公开(公告)日：2021-06-10

申请号：US16746444

申请日：2020-01-17

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Dino COSTANZO ,  Cheng Pan CAI ,  Xi Yu XU

IPC: G01R19/25 ,  G01R15/14 ,  H02P27/08 ,  H02M1/00 ,  H02M7/5387

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.