公开(公告)号：US20040054514A1

公开(公告)日：2004-03-18

申请号：US10447776

申请日：2003-05-29

Applicant: STMicroelectronics SA

Inventor： Philippe Flatresse ,  Mario Casu

IPC: G06F017/50 ,  H03K019/20

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

Abstract translation: 用于表征部分耗尽的绝缘体上硅类型（PD-SOI）的CMOS逻辑单元的方法可以包括对动态平衡状态下的逻辑单元建模并确定单元的晶体管的内部电位，该功能模拟基于 建模细胞。 这可以使用具有初始逻辑值的二进制刺激信号来完成。 动态平衡状态可以基于在刺激信号的两个连续转换周期内所采用的晶体管的浮动基板中的电荷量的变化平方和的精度误差内的抵消。