公开(公告)号：US20220318628A1

公开(公告)日：2022-10-06

申请号：US17714677

申请日：2022-04-06

申请人： Sai Kiran Cherupally ,  Jian Meng ,  Shihui Yin ,  Deliang Fan ,  Jae?sun Seo

发明人： Sai Kiran Cherupally ,  Jian Meng ,  Shihui Yin ,  Deliang Fan ,  Jae?sun Seo

IPC分类号： G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F7/544

摘要： Hardware noise-aware training for improving accuracy of in-memory computing (IMC)-based deep neural network (DNN) hardware is provided. DNNs have been very successful in large-scale recognition tasks, but they exhibit large computation and memory requirements. To address the memory bottleneck of digital DNN hardware accelerators, IMC designs have been presented to perform analog DNN computations inside the memory. Recent IMC designs have demonstrated high energy-efficiency, but this is achieved by trading off the noise margin, which can degrade the DNN inference accuracy. The present disclosure proposes hardware noise-aware DNN training to largely improve the DNN inference accuracy of IMC hardware. During DNN training, embodiments perform noise injection at the partial sum level, which matches with the crossbar structure of IMC hardware, and the injected noise data is directly based on measurements of actual IMC prototype chips.