公开(公告)号：US20140049664A1

公开(公告)日：2014-02-20

申请号：US14063729

申请日：2013-10-25

Applicant: Samsung Electronics Co .. Ltd.

Inventor： Tae-ho LEE ,  Takafumi USUI

IPC: H04N5/235

CPC classification number: H04N5/2353 ,  G03B9/40 ,  H04N5/3532 ,  H04N5/3535 ,  H04N5/35581 ,  H04N5/374

Abstract: A method and apparatus for increasing a dynamic range of an image by using a first electronic shutter and a second electronic shutter of a camera is provided. The method includes initiating exposure of an image sensor by moving a first electronic front curtain according to a first control pulse signal of the first electronic shutter; moving a second electronic front curtain with respect to at least one pixel of the image sensor according to a second control pulse signal of the second electronic shutter; blocking the exposure of the image sensor by moving a mechanical rear curtain included in the camera; and acquiring, after blocking the exposure, a long exposure image using the first electronic front curtain and a short exposure image using the second electronic front curtain.

Abstract translation: 提供了一种通过使用第一电子快门和相机的第二电子快门来增加图像的动态范围的方法和装置。 该方法包括通过根据第一电子快门的第一控制脉冲信号移动第一电子前帘来启动图像传感器的曝光; 根据第二电子快门的第二控制脉冲信号相对于图像传感器的至少一个像素移动第二电子前帘; 通过移动相机中包含的机械后帘来阻止图像传感器的曝光; 并且在使用所述第一电子前帘和使用所述第二电子前帘的短曝光图像之后，在遮挡所述曝光之后获取长曝光图像。

公开(公告)号：US20200257840A1

公开(公告)日：2020-08-13

申请号：US16788924

申请日：2020-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In HUH ,  Jeong-hoon KO ,  Hyo-jin CHOI ,  Seung-ju KIM ,  Chang-wook JEONG ,  Joon-wan CHAI ,  Kwang-il PARK ,  Youn-sik PARK ,  Hyun-sun PARK ,  Young-min OH ,  Jun-haeng LEE ,  Tae-ho LEE

IPC: G06F30/33 ,  G06N3/08

Abstract: A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

公开(公告)号：US20240086603A1

公开(公告)日：2024-03-14

申请号：US18511605

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： In HUH ,  Jeong-hoon KO ,  Hyo-jin CHOI ,  Seung-ju KIM ,  Chang-wook JEONG ,  Joon-wan CHAI ,  Kwang-II PARK ,  Youn-sik PARK ,  Hyun-sun PARK ,  Young-min OH ,  Jun-haeng LEE ,  Tae-ho LEE

IPC: G06F30/33 ,  G06N3/08

CPC classification number: G06F30/33 ,  G06N3/08

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.