公开(公告)号：US20240187505A1

公开(公告)日：2024-06-06

申请号：US18381748

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younjeong CHO ,  Eunjung LEE ,  Taesoo KIM ,  Taehyeong LEE ,  Jinyoung BAE ,  Jooyeong LEE

IPC: H04L69/40 ,  H04L61/4511 ,  H04L65/60

CPC classification number: H04L69/40 ,  H04L61/4511 ,  H04L65/60

Abstract: An electronic apparatus including a memory configured to store at least one instruction, and at least one processor configured to execute the at least one instruction to obtain metadata corresponding to a content providing channel and a streaming Uniform Resource Identifier (URI) corresponding to streaming of content from a content providing server, transmit the metadata and the streaming URI to a client apparatus, and based on a streaming error of a first server being occurred while the client apparatus streams the content from the first server using the streaming URI, transmit, to an external server, a signal corresponding to a request for mapping a second server to the streaming URI so that the client apparatus streams from the second server.

公开(公告)号：US20230039914A1

公开(公告)日：2023-02-09

申请号：US17742862

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun CHOI ,  Eunjung LEE ,  Junho LEE ,  Seungsoo HA

IPC: H01L23/66 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498

Abstract: Provided is a semiconductor package including a pair of differential signal wiring lines including a first differential signal wiring line and a second differential signal wiring line, extending parallel to and spaced apart from each other, a lower equal potential plate in a lower wiring layer under the signal wiring layer, an upper equal potential plate in an upper wiring layer above the signal wiring layer, and a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate, the wiring insulating layer filling spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, at least one of the lower equal potential plate and the upper equal potential plate including an impedance opening overlapping the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.