公开(公告)号：US20210057030A1

公开(公告)日：2021-02-25

申请号：US16987618

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Daehyun KIM ,  Guyeon WEI

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C7/10

Abstract: A semiconductor device is provided. The device includes a memory that stores data in a non-volatile and volatile manner and a memory controller configured to control the memory. The memory includes a word line pair including a first and second word line, a first bit line pair orthogonal to the first and the second word line and including a first bit line and a first complementary bit line, and a memory cell pair including first and second memory cells adjacent to the first memory cell in a word line direction. A left node of the first memory cell, and a right node of the first memory cell and a left node of the second memory cell, are all connected to the first word line, and a value of the data stored in the memory cell pair in the non-volatile manner is determined according to the selected first word line.

公开(公告)号：US20210034568A1

公开(公告)日：2021-02-04

申请号：US16936965

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyounghoon KIM ,  Gyeonghoon KIM ,  Hyunsik KIM ,  Haksup SONG ,  Guyeon WEI ,  Jonghun LEE ,  Jinsae JUNG ,  Junguk CHO ,  Sangbok HAN

IPC: G06F15/80 ,  G06F9/50

Abstract: A processor is provided. The processor includes a plurality of processing elements configured to be arranged in a matrix form, and a controller configured to control the plurality of processing elements during a plurality of cycles to process a target data, control first processing elements so that each of the first processing elements operates data provided from adjacent first processing elements and the input first element and inputs each of second elements included in a second row among the plurality of elements to second processing elements arranged in the second row among the plurality of processing elements, control the second processing elements so that each of the second processing elements operates data provided from adjacent second processing elements and the input second element, and operates data provided from the adjacent first processing elements in the same column among the first processing elements and pre-stored operation data.