公开(公告)号：US20230034533A1

公开(公告)日：2023-02-02

申请号：US17726370

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin LEE ,  Hoonmin KIM

IPC: H01L27/108 ,  H01L49/02

Abstract: A semiconductor device may include lower electrodes on a substrate, a first upper support layer pattern on upper sidewalls of the lower electrodes, and a dielectric layer and an upper electrode on surfaces of the lower electrodes and the first upper support layer pattern. The lower electrodes may be in a honeycomb pattern with the lower electrodes are at vertexes and center of a hexagon. The first upper support layer pattern may be a first plate shape including openings exposing some of all the lower electrodes. The lower electrodes may form rows in a first direction, the rows arranged in a second direction perpendicular to the first direction. Each opening may expose portions of upper sidewalls of at least four lower electrodes in two adjacent rows. Each of the openings may have a longitudinal direction in the first direction. In semiconductor devices, defects from bending stresses may be decreased.