公开(公告)号：US20180032658A1

公开(公告)日：2018-02-01

申请号：US15643472

申请日：2017-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naya HA ,  Yong-Durk KIM ,  Bong-hyun LEE ,  Hyung-ock KIM ,  Kwang-ok JEONG ,  Jae-hoon KIM

IPC: G06F17/50

Abstract: A system and method of designing an integrated circuit (IC) by considering a local layout effect are provided. The method of designing an IC may place instances of pre-placement cells so as to decrease occurrence of a local layout effect (LLE) causing structure. The method may extract a context of an instance from a peripheral layout of each of the placed instances to estimate an LLE of the instance, thereby analyzing a performance of the IC.