MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER

    公开(公告)号:US20250103209A1

    公开(公告)日:2025-03-27

    申请号:US18891579

    申请日:2024-09-20

    Inventor: Insoo KIM

    Abstract: A memory system includes a memory device, and a memory controller connected to the memory device. The memory controller is configured to analyze a pattern of the suspend schedule command a plurality of times to obtain a plurality of analysis results, select an operating mode from among a plurality of operating modes based on the plurality of analysis results, determine a suspend schedule based on the operating mode, and perform a memory operation on the memory device based on the suspend schedule. The plurality of operating modes including a latency mode and a throughput mode. The memory operation including at least one of a read operation or a write operation.

    METHOD AND APPARATUS WITH ACCESS AUTHORITY MANAGEMENT

    公开(公告)号:US20250045371A1

    公开(公告)日:2025-02-06

    申请号:US18920277

    申请日:2024-10-18

    Abstract: A method with access authority management includes: receiving an input image comprising a region of at least one portion of a body of a user; determining whether the user corresponds to multiple users or a single user using the region of the at least one portion of the body; performing a verification for the user based on a face region in the input image, in response to the determination that the user is the single user; determining whether the input image is a real image or a spoofed image based on whether the verification is successful; and allowing an access authority to a system to the user, in response to the determination that the input image is the real image.

    METHOD AND APPARATUS WITH ACCESS AUTHORITY MANAGEMENT

    公开(公告)号:US20230037263A1

    公开(公告)日:2023-02-02

    申请号:US17671747

    申请日:2022-02-15

    Abstract: A method with access authority management includes: receiving an input image comprising a region of at least one portion of a body of a user; determining whether the user corresponds to multiple users or a single user using the region of the at least one portion of the body; performing a verification for the user based on a face region in the input image, in response to the determination that the user is the single user; determining whether the input image is a real image or a spoofed image based on whether the verification is successful; and allowing an access authority to a system to the user, in response to the determination that the input image is the real image.

    METHOD AND APPARATUS WITH FACIAL IMAGE GENERATING

    公开(公告)号:US20220058377A1

    公开(公告)日:2022-02-24

    申请号:US17208048

    申请日:2021-03-22

    Abstract: A processor-implemented facial image generating method includes: determining a first feature vector associated with a pose and a second feature vector associated with an identity by encoding an input image including a face; determining a flipped first feature vector by flipping the first feature vector with respect to an axis in a corresponding space; determining an assistant feature vector based on the flipped first feature vector and rotation information corresponding to the input image; determining a final feature vector based on the first feature vector and the assistant feature vector; and generating an output image including a rotated face by decoding the final feature vector and the second feature vector based on the rotation information.

    STORAGE DEVICE, STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE CONTROLLER

    公开(公告)号:US20240211176A1

    公开(公告)日:2024-06-27

    申请号:US18392471

    申请日:2023-12-21

    CPC classification number: G06F3/0659 G06F3/0613 G06F3/0688

    Abstract: A storage controller includes: (i) a queue monitoring circuit configured to generate monitoring information about a queue depth (QD) for each of a write command and a read command, (ii) a surge detection circuit configured to generate command-by-command surge information based on the monitoring information, (iii) a priority determination circuit configured to generate priority determination information indicating any one of the write command, the read command, and a default according to the command-by-command surge information, and (iv) a priority reflection circuit configured to variably set each of a priority of the write command and a priority of the read command according to the priority determination information.

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