公开(公告)号：US20250133733A1

公开(公告)日：2025-04-24

申请号：US18886045

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyesung PARK ,  Jonghyuk PARK ,  Seungji KANG ,  Seongeun KIM ,  Jinwoo BAE ,  Dongwon LEE ,  Juyeon HAN

IPC: H10B12/00

Abstract: A semiconductor device may include a substrate with a memory cell area including a first active area and a peripheral circuit area including a second active area, a capacitor structure including a first electrode connected to the first active area in the memory cell area, a second electrode including a silicon containing layer surrounding the first electrode on the memory cell area and a metal plate layer on the silicon containing layer, an interlayer insulating layer on the peripheral circuit area, and a capping insulating layer covering the capacitor structure on the memory cell area and covering the interlayer insulating layer on the peripheral circuit area. The capacitor structure may include a capacitor dielectric layer between the first and second electrode. The metal plate layer may be on an upper surface of the silicon containing layer and may not be on a side surface of the silicon containing layer.