公开(公告)号：US20240404918A1

公开(公告)日：2024-12-05

申请号：US18397367

申请日：2023-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joong Suk OH ,  Ho Young KIM ,  Ki Ho BAE

IPC: H01L23/48 ,  H01L21/762 ,  H01L29/06

Abstract: There is provided a semiconductor device in which thickness variation of a substrate is precisely controlled. The semiconductor device includes a substrate comprising cell regions, a dummy region between the cell regions, an upper surface and a lower surface opposite the upper surface in a first direction, an active pattern disposed on the upper surface of the substrate, the active pattern comprising a lower pattern extending in a second direction crossing the first direction and a plurality of sheet patterns spaced apart in the first direction from each other, the plurality of sheet patterns being disposed in the cell region, a source/drain pattern disposed between the gate structures adjacent to each other, and a buried insulating pattern penetrating the substrate and the lower pattern in the dummy region.

公开(公告)号：US20180166343A1

公开(公告)日：2018-06-14

申请号：US15646300

申请日：2017-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Ho BAE ,  Jaeseok KIM ,  Hoyoung KIM ,  Boun YOON ,  KyungTae LEE ,  Kwansung KIM ,  Eunji PARK

IPC: H01L21/8234

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.