FPGA ACCELERATION SYSTEM FOR MSR CODES
    1.
    发明公开

    公开(公告)号:US20230367675A1

    公开(公告)日:2023-11-16

    申请号:US18223019

    申请日:2023-07-17

    CPC classification number: G06F11/1076 G06F13/28

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

    FPGA ACCELERATION SYSTEM FOR MSR CODES

    公开(公告)号:US20210334162A1

    公开(公告)日:2021-10-28

    申请号:US17367315

    申请日:2021-07-02

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

Patent Agency Ranking