公开(公告)号：US20150302822A1

公开(公告)日：2015-10-22

申请号：US14618333

申请日：2015-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha Jun LEE ,  Myung Ho SEO ,  Jin Han KIM ,  Suk Yun WOO ,  Seong Jong YOO

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2330/021 ,  G09G2330/06 ,  G09G2340/0435 ,  G09G2370/10

Abstract: A display driver integrated circuit (IC) includes a first driver block, a second driver block, and a transmission control circuit. The transmission control circuit is configured to deserialize pixel data groups of a serial data packet and to alternate sending the deserialized pixel data groups to the first driver block and the second driver block. Each of the pixel data groups includes pixel data for at least one pixel.

Abstract translation: 显示驱动器集成电路（IC）包括第一驱动器块，第二驱动器块和发送控制电路。 发送控制电路被配置为对串行数据分组的像素数据组进行反序列化，并且将反序列化的像素数据组交替发送到第一驱动器块和第二驱动器块。 每个像素数据组包括至少一个像素的像素数据。

公开(公告)号：US20140062995A1

公开(公告)日：2014-03-06

申请号：US14015166

申请日：2013-08-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Yang Wook KIM ,  Suk Yun WOO ,  Jun Ho SONG ,  Seong Jong YOO ,  Dong Min LEE ,  Kyung Gyu PARK ,  Hyung Woo YU

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0294 ,  G09G2310/0297

Abstract: A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.

Abstract translation: 提供了一种通过使用具有不同定时的时钟信号和执行该方法的装置对数据进行多路复用的方法。 同时执行数据的存储和复用（或分割）。 该装置包括：第一锁存电路，其响应于不重叠的锁存控制信号并行输入串行输入的数据块;以及第二锁存电路，其响应于时钟信号同时锁存并行排列的数据块。