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公开(公告)号:US20240173710A1
公开(公告)日:2024-05-30
申请号:US18319760
申请日:2023-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Su Keun KUK , Hyun Chul LEE , Sang Min JI , Sungwoo KANG , Dong Sik YANG
CPC classification number: B01J35/004 , A61L9/205 , B01J35/0013 , B01J35/023 , A61L2101/02
Abstract: A p-n heterojunction photocatalyst, an air purifier including the p-n heterojunction photocatalyst, and a method of preparing the p-n heterojunction photocatalyst. The p-n heterojunction photocatalyst includes a granule type composite which includes: first compound particles; and second compound particles on at least a portion of surfaces of the first compound particles, wherein the composite has a size of about 0.9 μm to about 5 μm based on a major axis, a standard deviation of the size is about ±0.9 μm or less, and upon exposure to energy irradiation, the composite generates a reactive oxygen species of singlet oxygen (1O2) to induce photolysis of gaseous pollutants.
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公开(公告)号:US20210217749A1
公开(公告)日:2021-07-15
申请号:US16888209
申请日:2020-05-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sanghyun LEE , Sungwoo KANG , Jongchul PARK , Youngmook OH , Jeongyun LEE
IPC: H01L27/088 , H01L21/768 , H01L29/417
Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.
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