公开(公告)号：US20140129894A1

公开(公告)日：2014-05-08

申请号：US14070000

申请日：2013-11-01

Applicant: Sirius XM Radio Inc.

Inventor： Richard Gerald Branco ,  Edward Schell

IPC: H03M13/11

CPC classification number: H03M13/1111 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/3746 ,  H03M13/6516

Abstract: Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.

Abstract translation: 提供了适用于一系列码块大小和比特率的LDPC解码器的新颖设计，也适用于ASIC和FPGA实现，其中与传输信道发送的校正数据相关联的开销可以最小化。 可以针对基于eIRA或一般H矩阵优化LDPC解码器。 可以构造和/或操纵H奇偶校验矩阵以排列比特节点消息“列”以便于映射到MPB“列”以及经由LUT指针表的对应访问以最小化处理周期，以便：（i）最小化地址冲突 在同一个MPB中，将采取多个访问周期来解决; （ii）最大限度地减少跨越将需要多个访问周期来解决的MPB“列”的位节点消息; 并且（iii）平衡所有MPB / LUT“列”上的位节点计算，使得它们将在几乎相同的时间完成它们的计算。

公开(公告)号：US20160056841A1

公开(公告)日：2016-02-25

申请号：US14837026

申请日：2015-08-27

Applicant: Sirius XM Radio Inc.

Inventor： Richard Gerald Branco ,  Edward Schell

IPC: H03M13/11 ,  H03M13/37

CPC classification number: H03M13/1111 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/3746 ,  H03M13/6516

Abstract: Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.

Abstract translation: 提供了适用于一系列码块大小和比特率的LDPC解码器的新颖设计，也适用于ASIC和FPGA实现，其中与传输信道发送的校正数据相关联的开销可以最小化。 可以针对基于eIRA或一般H矩阵优化LDPC解码器。 可以构造和/或操纵H奇偶校验矩阵以排列比特节点消息“列”以便于映射到MPB“列”以及经由LUT指针表的对应访问以最小化处理周期，以便：（i）最小化地址冲突 在同一个MPB中，将采取多个访问周期来解决; （ii）最大限度地减少跨越将需要多个访问周期来解决的MPB“列”的位节点消息; 并且（iii）平衡所有MPB / LUT“列”上的位节点计算，使得它们将在几乎相同的时间完成它们的计算。

公开(公告)号：US09160366B2

公开(公告)日：2015-10-13

申请号：US14070000

申请日：2013-11-01

Applicant: Sirius XM Radio Inc.

Inventor： Richard Gerald Branco ,  Edward Schell

IPC: H03M13/00 ,  H03M13/11

CPC classification number: H03M13/1111 ,  H03M13/1105 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/3746 ,  H03M13/6516

Abstract: Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.

Abstract translation: 提供了适用于一系列码块大小和比特率的LDPC解码器的新颖设计，也适用于ASIC和FPGA实现，其中与传输信道发送的校正数据相关联的开销可以最小化。 可以针对基于eIRA或一般H矩阵优化LDPC解码器。 可以构造和/或操纵H奇偶校验矩阵以排列比特节点消息“列”以便于映射到MPB“列”以及经由LUT指针表的对应访问以最小化处理周期，以便：（i）最小化地址冲突 在同一个MPB中，将采取多个访问周期来解决; （ii）最大限度地减少跨越将需要多个访问周期来解决的MPB“列”的位节点消息; 并且（iii）平衡所有MPB / LUT“列”上的位节点计算，使得它们将在几乎相同的时间完成它们的计算。