公开(公告)号：US20240248775A1

公开(公告)日：2024-07-25

申请号：US18603003

申请日：2024-03-12

Applicant: Snap Inc.

Inventor： Amirreza Yousefzad ,  Arash Pourtaherian ,  Peng Qiao ,  Orlando Miguel Pires dos Reis Moreira ,  Luc Johannes Wilhelmus Waeijen

IPC: G06F9/54

CPC classification number: G06F9/546 ,  G06F9/542

Abstract: A message-based processing system is disclosed. An input message received in the message-based processing system comprises a first indication of at least a subset of a plurality of processor elements and a second indication of a target pattern. Each of the plurality of processor elements has an addressable storage entry with a processor element address storing a processor element state. An initial address computation mode is selected from a set of address computation modes. A state value of each of the processor elements in the subset is updated based on magnitude values of respective pattern elements of the target pattern. A currently applied pattern element of the target pattern in each case determines whether to maintain a current address computation mode of the set of address computation modes or assume a next address computation mode selected from the set of address computation modes.

公开(公告)号：US11960946B2

公开(公告)日：2024-04-16

申请号：US17787203

申请日：2020-12-18

Applicant: Snap Inc.

Inventor： Amirreza Yousefzadeh ,  Arash Pourtaherian ,  Peng Qiao ,  Orlando Miguel Pires Dos Reis Moreira ,  Luc Johannes Wilhelmus Waeijen

IPC: G06F9/54

CPC classification number: G06F9/546 ,  G06F9/542

Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

公开(公告)号：US12288109B2

公开(公告)日：2025-04-29

申请号：US18603003

申请日：2024-03-12

Applicant: Snap Inc.

Inventor： Amirreza Yousefzadeh ,  Arash Pourtaherian ,  Peng Qiao ,  Orlando Miguel Pires dos Reis Moreira ,  Luc Johannes Wilhelmus Waeijen

IPC: G06F9/54

Abstract: A message-based processing system is disclosed. An input message received in the message-based processing system comprises a first indication of at least a subset of a plurality of processor elements and a second indication of a target pattern. Each of the plurality of processor elements has an addressable storage entry with a processor element address storing a processor element state. An initial address computation mode is selected from a set of address computation modes. A state value of each of the processor elements in the subset is updated based on magnitude values of respective pattern elements of the target pattern. A currently applied pattern element of the target pattern in each case determines whether to maintain a current address computation mode of the set of address computation modes or assume a next address computation mode selected from the set of address computation modes.